A memory array comprises a plurality of memory cells, or cells, and is organized into rows and columns of such cells. A column extends over the matrix in a vertical direction, whereas a row extends over the matrix in a horizontal direction. The cell that lies at the ith row and the jth column is called the i,j cell. The cells of a same column have a same j index, the i index varying from 1 to the number of rows of the matrix. The cells of a same row have a same i index, the j index varying from 1 to the number of columns of the matrix.
Each cell may comprise one or more storing elements, e.g., transistor(s) and/or capacitor(s). Each cell may be coupled to a number of control lines, e.g., one source line, one word line and one bit line. The control lines are conductive, e.g., metallic lines, which are typically coupled to one or more transistor(s) of the cell, via their source, gate or drain terminals for example.
Addressable bit lines may be coupled to the cells in a corresponding column of cells, and the cells in any row of cells may be coupled to a corresponding pair of addressable word and source lines. The control lines hence allow selecting any cell of the array and reading from or writing to the selected cell.
The words may typically comprise 8, 16, 32, 64, 128 or 256 bits, i.e., each word line is coupled to 8, 16, 32, 64, 128 or 256 cells respectively. As the number of cells in a row increases, the electrons in the word line or in the source line have to move over an increasingly long path. Furthermore, the dimensions of the semiconductor array tend to shrink, i.e., the section of the control line crossed by the electrons becomes smaller and smaller. The cells may therefore be relatively difficult to control in read and/or write mode.